This invention relates to an apparatus for testing semiconductor chips on an uncut wafer containing unseparated die prior to packaging or on an array of separate integrated circuit (IC) chips. More particularly, this invention relates to parallel testing of IC chips over all or substantially all of an uncut wafer. The invention could also be used for testing a plurality of circuits in parallel which are mounted on a substrate, such as hybrid circuits.
Semiconductor manufacturers are now producing semiconductor wafers with hundreds or even thousands of integrated circuits per wafer. As device geometries decrease and the size of the semiconductor wafers increase, the number of integrated circuit dies formed on each wafer is continuing to increase. Consequently, wafer level testing has become a widely accepted method for screening out defective ICs as early as possible in the manufacturing process.
In some wafer scale testing equipment, a number of probes are placed in contact with selected regions of a particular wafer under test. In some test equipment, a probe is contacted to each bonding pad on an individual die. Using computer controlled testing equipment, voltages are generated at the probe tips, thereby testing a certain number of ICs from a given wafer. Typically such a procedure involves testing each die in order to determine whether each die passes basic electrical tests, such as a test for electrical opens or electrical shorts. In some applications, a functional test is also performed using the probe equipment to ensure that the ICs performs as designed. As demands for the number of elements of a circuit or a wafer to be tested increase, the strains on testing equipment become evident. However, the number of contact probes cannot be increased easily because the net force loading of contact probes against a surface increases with the total number of probes, which can cause numerous problems.
FIG. 1 is a simplified side cross-sectional view of a portion of a wafer probe head of the prior art showing an unloaded configuration. In FIG. 1, a number of probe tips 2 are mounted on a multi-layer ceramic substrate 4 fabricated from co-fired alumina. The ceramic substrate is mounted on a printed circuit board 6 by a clamping mechanism (not shown) or by other means. Connection between the probe tips 2 and the printed circuit board 6 is provided by spring wires 8. As illustrated in FIG. 1, the support of the probe tip structure is limited to the periphery of the ceramic substrate.
FIG. 2 is a simplified side cross-sectional view of a portion of a wafer probe head of the prior art under a load. As illustrated in FIG. 2, loading from a contact force is illustrated by force F and the arrows directed toward the probe tips. Under load, the ceramic substrate warps as illustrated. In some high density applications, the substrate warpage approaches a displacement on the same level as the displacement range of the probe tips themselves. As a consequence, the probe tips do not make uniform or reliable contact with the wafer under test or device under test (DUT). What is needed is a more reliable probe head that is resistant to substrate warpage.